1. Field of the Invention
The present invention relates to a semiconductor device suitable for preventing film peeling due to dicing and for restraining abnormal discharge during etching.
2. Description of the Related Art
Dicing technology, which divides a semiconductor wafer into semiconductor chips, is indispensable for producing semiconductor chips. However, film peeling sometimes occurs due to an impact of dicing or handling of the semiconductor chip after dicing. FIGS. 3A and 3B are cross-sectional views illustrating a problem of film peeling inherent in a conventional semiconductor device. FIG. 3A illustrates a cross-sectional view before dicing and FIG. 3B illustrates a cross-sectional view after dicing. In a structure having an inter-layer insulating film 002 deposited on a semiconductor substrate 001, dicing along a scribe region 003 between pluralities of IC regions 004 causes damage due to penetration from each end surface of semiconductor chips in contact with a region 006 which is cut and removed by dicing. Then, the laminated inter-layer insulating film 002 peels off from the semiconductor substrate 001 as illustrated in FIG. 3B, with the result that a film peeling portion 005 may appear even in the IC region 004.
As a method for preventing the film peeling caused by dicing, physical separation of the films deposited on the semiconductor substrate is offered (see, for example, Japanese Patent Application Laid-open No. H01-309351). FIGS. 4A and 4B are cross-sectional views of a semiconductor device which employs the above-mentioned method to take measures against film peeling. FIG. 4A illustrates a cross-sectional view before dicing and FIG. 4B illustrates a cross-sectional view after dicing. Separation grooves 007 are provided in the inter-layer insulating film 002 in the vicinity of boundaries between the scribe region 003 and the IC regions 004, so as to physically separate the inter-layer insulating films 002 between the respective regions. When dicing is performed as illustrated in FIG. 4B, the inter-layer insulating films 002 in the vicinity of the end surfaces of the semiconductor chips in contact with the cut and removed region 006 are damaged to peel off and scatter from the semiconductor substrate 001 as small pieces 008, whereas no damage propagates through portions without the inter-layer insulating films 002, causing no peeling of the inter-layer insulating films 002 in the IC regions 004.
However, the applicant has found through research that the following problem arises if the above-mentioned conventional technology is applied to a semiconductor device having a metal plug. FIGS. 5A to 5D are cross-sectional views illustrating a difficulty which occurs when the conventional technology and the plug technology are used in combination. FIG. 5A illustrates a cross section in which the separation groove 007 is provided in the inter-layer insulating film 002 on the semiconductor substrate 001, and a plug metal film 010 is thereafter deposited on the inter-layer insulating film 002 and an exposed part of the semiconductor substrate 001. A contact hole 009 with a small opening is completely filled with the plug metal film 010, whereas the separation groove 007 with a large opening is not filled with the metal film but the plug metal film 010 is deposited along a bottom part and lateral walls of the separation groove 007. FIG. 5B illustrates a cross section after the deposited plug metal film 010 is etched back, illustrating side walls 011 of the plug metal films formed as lateral walls of the separation groove 007. FIG. 5C illustrates a cross section after metal wiring 012 is formed and connected to the plug metal film inside the contact hole 009 and a passivation film 013 is then deposited over a semiconductor wafer. FIG. 5D illustrates a cross section when etching for pad opening is performed with the IC region 004 covered with a′pad etching resist 014. It has been found that, when a part of the passivation film 013 is removed by etching to expose the underlayer, abnormal discharge 015 is generated on the side wall 011 of the plug metal film, resulting in a difficulty of wafer surface burning. It has been recognized that the difficulty described above needs to be further addressed.